An update for microcode_ctl is now available for openEuler-20.03-LTS-SP1 Security Advisory openeuler-security@openeuler.org openEuler security committee openEuler-SA-2023-1548 Final 1.0 1.0 2023-08-26 Initial 2023-08-26 2023-08-26 openEuler SA Tool V1.0 2023-08-26 microcode_ctl security update An update for microcode_ctl is now available for openEuler-20.03-LTS-SP1. This is a tool to transform and deploy microcode update for x86 CPUs. Security Fix(es): Incorrect default permissions in some memory controller configurations for some Intel(R) Xeon(R) Processors when using Intel(R) Software Guard Extensions which may allow a privileged user to potentially enable escalation of privilege via local access.(CVE-2022-33196) Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software Guard Extensions may allow a privileged user to potentially enable information disclosure via local access.(CVE-2022-38090) Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.(CVE-2022-40982) An update for microcode_ctl is now available for openEuler-20.03-LTS-SP1. openEuler Security has rated this update as having a security impact of medium. A Common Vunlnerability Scoring System(CVSS)base score,which gives a detailed severity rating, is available for each vulnerability from the CVElink(s) in the References section. Medium microcode_ctl https://www.openeuler.org/en/security/safety-bulletin/detail.html?id=openEuler-SA-2023-1548 https://www.openeuler.org/en/security/cve/detail.html?id=CVE-2022-33196 https://www.openeuler.org/en/security/cve/detail.html?id=CVE-2022-38090 https://www.openeuler.org/en/security/cve/detail.html?id=CVE-2022-40982 https://nvd.nist.gov/vuln/detail/CVE-2022-33196 https://nvd.nist.gov/vuln/detail/CVE-2022-38090 https://nvd.nist.gov/vuln/detail/CVE-2022-40982 openEuler-20.03-LTS-SP1 microcode_ctl-2.1-41.oe1.src.rpm microcode_ctl-2.1-41.oe1.x86_64.rpm Incorrect default permissions in some memory controller configurations for some Intel(R) Xeon(R) Processors when using Intel(R) Software Guard Extensions which may allow a privileged user to potentially enable escalation of privilege via local access. 2023-08-26 CVE-2022-33196 openEuler-20.03-LTS-SP1 Medium 6.7 AV:L/AC:L/PR:H/UI:N/S:U/C:H/I:H/A:H microcode_ctl security update 2023-08-26 https://www.openeuler.org/en/security/safety-bulletin/detail.html?id=openEuler-SA-2023-1548 Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software Guard Extensions may allow a privileged user to potentially enable information disclosure via local access. 2023-08-26 CVE-2022-38090 openEuler-20.03-LTS-SP1 Medium 4.4 AV:L/AC:L/PR:H/UI:N/S:U/C:H/I:N/A:N microcode_ctl security update 2023-08-26 https://www.openeuler.org/en/security/safety-bulletin/detail.html?id=openEuler-SA-2023-1548 Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. 2023-08-26 CVE-2022-40982 openEuler-20.03-LTS-SP1 Medium 6.5 AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N microcode_ctl security update 2023-08-26 https://www.openeuler.org/en/security/safety-bulletin/detail.html?id=openEuler-SA-2023-1548